The present invention relates to semiconductor memory devices, and, more particularly, to a structure and method of preventing trenching in the fabrication of self-aligned split gate flash devices.
A split gate flash memory device is essentially a MOS transistor with a variable threshold voltage. The threshold voltage varies with the amount of charge that is stored on a floating gate structure. The floating gate structure overlies a first part of the device channel region. A control gate structure overlies a second part of the device channel region. Voltage on the control gate controls the second part of the device channel region directly and controls the first part of the device channel indirectly, as modulated by charge on the floating gate. The control gate is formed in close proximity to the floating gate so that a capacitive coupling between the control gate and the floating gate is achieved.
Flash memories have undergone significant improvements over the years, such as dramatic reduction of device size. As devices reduce in size, however, a number of problems may occur. One such problem is the formation of trenches in the active areas of the devices during a floating gate polysilicon etching step. This problem is best explained by way of description and illustration. FIGS. 1–10 show the present state of manufacturing a partially completed split gate flash device. Referring to FIG. 1, a top view of a partially completed split gate flash memory is shown. A typical flash memory comprises a very large number, perhaps millions, of identical memory cells. The cells are arranged in a two-dimensional array to facilitate addressing, reading, and writing to specific cells in the array.
In this layout, a semiconductor substrate 10 is provided. The substrate 10 is divided into two types of areas: active 10 and isolation 20. The active areas (OD) 10 are simply areas of semiconductor. The isolation areas (STI) 20 are areas where a dielectric material has been formed. The isolation areas 20 may comprise any type of dielectric material and structure suitable for isolating adjacent active devices, such as shallow trench isolation (STI) that may be formed by well-known methods. Typically, STI regions 20 comprise trenches in the substrate 10 that are filled with a dielectric material such as silicon oxide. The memory array is laid out such that the STI regions 20 and active (OD) regions 10 (active region 10 is not shown but a first patterned masking layer of silicon nitride (SiN) 50 overlying active region 10 is shown instead) are in parallel. Two cross sections “2” and “9” are analyzed in the description below. The “2” cross section bisects the parallel STI 20 and SiN 50 regions. The “9” cross section is parallel to the STI 20 and SiN regions 50.
Referring now to FIG. 2, the “2” cross section is illustrated and several layers are formed overlying the substrate 10. A dielectric layer 30 is formed overlying the substrate 10. This dielectric layer 30 is the floating gate dielectric and may comprise any dielectric layer having suitable dielectric constant and breakdown capability.
A conductor layer 40 is then grown overlying the dielectric layer 30. The conductive layer may comprise any conductive material, such as a metal, a semiconductor, or a combination of both, that can be used in the formation of a MOS gate. A first masking layer 50 is then deposited overlying the conductor layer 40. A photoresist layer (not shown) is then deposited over the masking layer 50 and using a conventional photolithography process, the photoresist layer is patterned and etched to form a pattern of openings. The photoresist pattern is normally used to protect all areas on which active devices will later be formed. Thereafter, the masking layer 50, conductor layer 40, dielectric layer 30 and substrate 10 are etched according to the pattern of openings in the photoresist layer and a plurality of isolation trenches defined by masking layer 50 are formed in the substrate 10. The masking layer 50 and conductor layer 40 may be dry etched, and the dielectric layer 30 may be etched by means of either a dry- or wet-chemical process, as is well-known in the art. The etching is further carried into the substrate 10 to form trenches. The trenches are thereafter filled by an STI oxide material and may be filled by well-known methods such as high density plasma CVD (HDPCVD). The STI oxide material is thereafter planarized by conventional CMP (chemical mechanical planarization) processes. Other planarization processes could also be used. As shown in FIG. 2, the substrate 10 is divided by a series of isolation (STI) regions 20, each isolation region separates an active cell area in the substrate.
FIG. 3 is a first cross sectional view of the structure of FIG. 2 showing the removal of the first masking layer 50 by conventional etching processes and the deposition of a second masking layer 60. Second masking layer 60 is the floating gate layer and may comprise of a material that can be selectively etched with respect to the underlying layers such as conductor layer 40. Second masking layer 60 may comprise silicon nitride that is deposited by chemical vapor deposition.
FIG. 4 is a second cross sectional view using the “9” of FIG. 1 of the split gate flash device showing a patterned photoresist layer 70, second masking layer 60, conductor layer 40, and the dielectric layer 30 formed over the substrate 10. After a conventional lithography process, FIG. 5 shows the second masking layer 60 etched and a portion of conductor layer 40 etched away and the removal of the patterned photoresist layer 70 by a conventional ashing process. Following the ashing step, an oxide material, such as TEOS 80, is deposited over second masking layer 60 and conductor layer 40 for subsequent spacer formation, as shown in FIG. 6. TEOS layer 80 is etched back to form spacers 90 on the sidewalls of the second masking layer 60, as shown in FIG. 7. This etch back step preferably comprises a dry etch having an anisotropic etching characteristic. FIG. 8 is a cross sectional view taken from “2” of FIG. 1 of the structure of FIG. 3 after the step of forming spacers showing corners of active regions (OD) 10 being exposed.
FIG. 9 is a cross sectional view taken from “9” of FIG. 1 of the structure of FIG. 7 showing the etching of the conductor layer 40 and partial etching of the dielectric layer 30. Conductor layer 40 is etched through where exposed by the second masking layer 60 and spacers 90.
The problem the present invention addresses is during the conventional formation of split gate flash devices where undesirable trenches are formed in the active areas of the devices during the floating gate polysilicon/conductor layer etching step. FIG. 10 is a cross sectional view taken from “2” of FIG. 1 of the structure of FIG. 8 after the etching of the conductor layer 40 and the formation of undesirable trenches 100 in the substrate. As shown in FIG. 8, STI regions 20 recesses after the floating gate TEOS spacer etching step which causes the corners of active regions (OD) 10 to become exposed. The exposed active regions 10 causes trenching after the etching of conductor layer 40. Trenches 100 affect product yield and performance of the split gate flash device.
Accordingly, what is needed in the art is a device and method of manufacture thereof that addresses the above-discussed issues.